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8 DC Analyses
Fi
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ure 9-4
Device Curve Family
Fi
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ure 9-5
Operating Point Determination for Each Member
of the Curve Family
- User’s Guide 1
- Simulation ExamplesChapter 2 4
- Part Two Desi 5
- ModelsChapter 4 6
- Symbols for ModelsChapter 5 7
- Chapter 6 8
- Chapter 7 9
- Contents 10
- AC AnalysesChapter 10 11
- Transient AnalysisChapter 11 11
- Contents xiii 13
- Part Four Viewin 15
- Results 15
- Before You Be 25
- MicroSim PSpice A/D 26
- Overview 26
- How to Use this Guide 27
- Related Documentation 28
- Online Help 29
- If You Don’t Have the 30
- Standard PSpice A/D 30
- If You Have the Evaluation 33
- What’s New 34
- BSIM3 version 3 MOSFET model 35
- Part One 36
- What is PSpice A/D? 38
- Basic Anal 39
- AC sweep and noise 40
- Transient and Fourier 41
- Advanced Multi-Run Anal 42
- Monte Carlo and sensitivit 43
- /worst-case 43
- Schematics to Prepare for 45
- Simulation 45
- What is the Stimulus Editor? 45
- What is the Parts Utilit 46
- What is Probe? 46
- Files Needed for 47
- Other Files That You Can 48
- Model librar 49
- Files That PSpice A/D 51
- Generates 51
- PSpice output file 52
- Simulation Examples 53
- Example Circuit 54
- Creation 54
- Connection Points 56
- Example Circuit Creation 2 57
- Bias Point Anal 58
- the Bias Information 59
- the Simulation Output File 61
- DC Sweep Anal 62
- DC Sweep Dialo 63
- 12 Simulation Examples 64
- To delete all of the traces 67
- Amplitude = 10 69
- Transient Analysis 70
- AC Sweep and 73
- Noise Analysis Dialo 73
- Parametric Dialog Box 78
- all 21 traces in Probe 79
- Probe Performance 82
- To plot 83
- Part Two 85
- Preparin 86
- a Schematic for 86
- Checklist for Simulation 87
- Using Schematic Markers to 88
- Add Traces on page 17-13 88
- Limiting Probe Data File 88
- Size on page 17-15 88
- For more information on 89
- Parts That You 92
- Can Simulate 92
- Vendor-Supplied Parts 93
- To find parts usin 95
- the online Librar 95
- Passive Parts 96
- Breakout Parts 97
- Behavioral Parts 98
- Global 99
- Parameters and 99
- Expressions for Values 99
- VSUPPLY 100
- {VSUPPLY} 100
- Expressions 101
- Table 3-1 102
- Operators in Expressions 102
- Table 3-2 103
- Power Supplies 106
- Stimuli 108
- VPWL_F_N_TIMES** 109
- Devices 110
- VSRC or ISRC s 111
- Stimuli 3 112
- Unmodeled Parts 113
- Library List or read the 114
- Unmodeled Pins 116
- Check for this 117
- DC Path to Ground 118
- and Editin 119
- What Are Models? 121
- How Are Models 122
- Local models 123
- Global models 123
- Nested Model Libraries 124
- MicroSim-Provided Models 124
- Tools to Create and Edit 125
- Parts-Supported Device T 130
- How to Fit Models 132
- To fit the model 133
- To view performance curves 133
- the Parts Utilit 134
- Parts utility supports. See 136
- for details 136
- What is an instance model? 138
- What happens if 140
- The Parts Utilit 141
- Tutorial 141
- Diode Model 142
- Values for the Dbreak-X 142
- the Model Editor 147
- Model Properties 148
- the Model Editor from 151
- Example: Editin 153
- a Q2N2222 153
- Instance Model 153
- the edits and updatin 154
- the schematic 154
- the Create 155
- Subcircuit Command 155
- Instance 157
- How PSpice A/D Uses Model 161
- Libraries 161
- search path 165
- Chapter Overview 166
- What’s Different About 168
- Simulation? 168
- ➥ Automatically create 169
- ➥ Produce a compact 169
- ➥ Automatically create one 169
- To set up a model librar 170
- How to Start the S 171
- How the S 172
- How to Create AKO S 174
- To confi 176
- 14 Creatin 179
- Symbols for Models 179
- How Schematics Places 180
- ✔ Does the value of the 183
- ✔ Does the TEMPLATE 183
- ✔ Are the pins/nodes in the 183
- ✔ Do the pin/node names in 183
- SIMULATION ONLY 184
- TEMPLATE 185
- Attribute names in templates 186
- The ^ character in templates 187
- IN+ OUT+ IN- OUT 190
- IO_LEVEL 192
- MNTYMXDLY 193
- IPIN attributes 194
- Behavioral Modelin 195
- Overview of Analo 196
- Behavioral Modelin 196
- ABM Expressions 198
- the Use of a Global 199
- Definition 199
- ABM Part Templates 200
- Control S 201
- Basic Components 203
- Limiters 204
- HIPASS Filter Part 206
- BANDPASS Filter 206
- Part Example 206
- BANDREJ Filter 207
- Table Look-Up Parts 208
- FTABLE Part 210
- + (6kHz,-60,-6912) 211
- + DELAY=3.2ms 211
- Laplace Transform Part 212
- LAPLACE Part 213
- Example 1 213
- Example 2 213
- Math Functions 215
- ABM Expression Parts 215
- ABM Expression 216
- Part Example 1 216
- Part Example 2 217
- Part Example 3 218
- Part Example 4 218
- An Instantaneous Device 219
- Example: Modelin 219
- a Triode 219
- Control System Parts 6 221
- PSpice A/D-Equivalent 222
- Implementation of PSpice A/D 223
- Equivalent Parts 223
- Mathematical or 224
- Instantaneous Relationships 224
- EVALUE Part 225
- GVALUE Part 225
- EMULT Part 226
- Lookup Tables (ETABLE and 227
- 34 Analo 228
- Frequenc 229
- -Domain Device 229
- Laplace Transforms (LAPLACE) 229
- Response Tables 231
- (EFREQ and GFREQ) 231
- EFREQ Part 232
- PSpice A/D-Equivalent Parts 6 233
- Instantaneous Device Modelin 234
- -Domain Parts 235
- Laplace Transforms 235
- -0.001·s 236
- Off Computer 239
- Resources For Accurac 239
- Basic Controlled 240
- Introduction 242
- Functional 243
- Behavior 243
- Table 7-1 244
- Functional Behavior 7 247
- + IO_STD 249
- Characteristics 251
- DIGMNTYSCALE 253
- DIGTYMXSCALE 253
- constraints 253
- Calculation 254
- Inertial and Transport Dela 255
- Transport dela 256
- Input/Output 257
- Characteristics 257
- and TSWHL 259
- Table 7-2 260
- Output Stren 261
- Controllin 263
- overdrive 263
- Pin-to-Pin Dela 273
- (PINDLY 273
- Primitive) 273
- Constraint Checker 276
- (CONSTRAINT Primitive) 276
- Setup_Hold 276
- The 74160 Example 277
- Part Three 281
- Parametric 284
- PSpice A/D Basics+ 284
- Up Anal 285
- Execution Order for Standard 286
- Output Variables 287
- Modifiers 288
- Up Analyses 8 289
- Table 8-4 290
- The IGBT device 291
- Simulation 293
- Method 1 295
- Method 2 295
- The Simulation Status Window 296
- Simulation pro 297
- DC Sweep 299
- DC Sweep Setup 299
- Overview of DC Sweep 300
- 4 DC Analyses 301
- Up a DC Stimulus 302
- Nested DC Sweeps 303
- Curve Family 304
- Example Schematic 304
- 8 DC Analyses 305
- Bias Point Detail 306
- Small-Si 308
- Transfer 308
- Overview of Small-Si 309
- DC Sensitivit 310
- Overview of DC Sensitivit 311
- AC Sweep Anal 313
- Up an AC Stimulus 314
- Magnitude_value [phase_value] 315
- Up an AC Anal 316
- AC Sweep Setup in 317
- “example.sch” 317
- How PSpice A/D Treats 318
- Nonlinear Devices 318
- 8 AC Analyses 319
- This is exactly how a double 319
- Noise Anal 320
- What is Noise Anal 321
- Up a Noise Anal 322
- Noise in Probe 323
- 14 AC Analyses 325
- To find out more about Probe 325
- Transient Anal 326
- Overview of Transient 327
- a Time-Based 328
- Stimulus 328
- The Stimulus Editor 330
- 6 Transient Analysis 331
- the Stimulus Editor 332
- Example: sine wave sweep 334
- New Stimulus S 335
- a Stimulus 337
- To manuall 338
- 14 Transient Analysis 339
- Transient (Time) 340
- Response 340
- Transient 340
- Internal Time Steps in 342
- Electronic 343
- Hysteresis Curves 11 344
- Fourier Components 345
- Fourier Components 11 346
- Parametric and Temperature 347
- Parametric Anal 348
- Overview of Parametric Anal 349
- Example: RLC Filter 349
- the simulation 350
- Parametric Analysis 12 353
- up the circuit 354
- CvF(-I(Vin)/V(1,0)) 355
- CvF(-I(Vin)/V(1)) 355
- Temperature Anal 357
- Statistical Anal 360
- Waveform Reports 362
- Collatin 362
- Functions 362
- Table 13-1 363
- Monte Carlo Anal 365
- Monte Carlo 365
- Tutorial: Monte Carlo Anal 368
- up the parameters 370
- R=1 DEV=5% 374
- Monte Carlo Histo 377
- Analysis Setup Example 378
- To displa 381
- the center frequenc 381
- Center Frequency Histogram 382
- Worst-Case Anal 383
- Procedure 384
- Worst-Case Analysis 13 385
- YatX Goal 387
- Schematic 390
- Demonstratin 390
- Use of VARY 390
- Manual optimization 392
- Monte Carlo anal 392
- MicroSim 395
- Schematics User’s Guide 395
- Concepts You Need to 396
- Understand 396
- Top-Level Interface Ports 399
- To add a transition 403
- To move a transition 403
- To edit a transition 403
- To set the default bus radix 406
- To add a loop 407
- To define a clock si 409
- DIGCLOCK 409
- the FILESTIM Device 411
- Adjustin 414
- Simulation Parameters 14 414
- the Simulation 415
- IN1 IN2 Q1 Q2 417
- To add a di 418
- Buses to a Probe Plot 419
- To add a bus expression 420
- Persistent hazards 421
- Analyzin 422
- Results 14 422
- Simulation condition messa 423
- Table 14-4 424
- Output control options 426
- Interface Subcircuit 429
- Selection b 429
- PSpice A/D 429
- Level 1 Interface 430
- Level 2 Interface 431
- the Default A/D Interface 432
- To create a custom di 435
- Interface Generation 438
- PSpice A/D representation 439
- + T_BUF IO_STD 444
- Critical Hazard 447
- Cumulative Ambi 449
- Reconver 450
- Glitch Suppression Due 452
- Methodolo 453
- Part Four 456
- Overview of Probe 458
- Elements of a Probe Plot 459
- Elements of a Plot Window 460
- Multiple Plot Windows 461
- Probe Colors 462
- Reference Manual 465
- Other Wa 468
- Schematic Markers to Add 469
- Probe Data File Size 471
- 16 Analyzin 472
- Waveforms in Probe 472
- Simulation Data from 474
- Multiple Files 474
- Appendin 475
- data files 475
- To append a data file 475
- Trace Le 476
- Simulation Results in 477
- ASCII Format 477
- Example 478
- Example.dat) 479
- 24 Analyzin 480
- About Di 481
- About the Oscillator Circuit 482
- Up the Schematic 482
- Mixed Analo 485
- User Interface Features 486
- To zoom in the analo 487
- area usin 487
- the mouse 487
- Scrollin 488
- To set the di 489
- To move labels 492
- User Interface Features 17 495
- Probe Trace 500
- Basic Output Variable Form 501
- Terminals 502
- Table 17-4 503
- Probe Output Variable Formats 503
- Table 17-5 505
- Table 17-6 505
- Output Variable AC Suffixes 505
- Table 17-7 506
- Table 17-8 507
- Device Type 507
- Table 17-9 508
- Noise Types by Device Type 508
- /Hz. This means 509
- /Hz, NTOT(ONOISE) 509
- Trace Expressions 510
- Probe Trace Expressions 17 511
- The Bias Information Toolbar 518
- Bias Point Volta 520
- Currents 521
- Label Associations 523
- colors for bias information 524
- If You Have Hierarchical 525
- Bias Point Values 526
- Run the simulation 527
- Other Output Options 528
- Additional 530
- Results to the 530
- PSpice Output File 530
- 4 Other Output Options 531
- PSpice A/D defaults to MAG 531
- Test Vector 533
- Initial State 534
- Save and Load Bias 535
- Load Bias Point 536
- Setpoints 537
- Setpoints A 538
- Initial 539
- Conditions 539
- Too Small Errors” 540
- V/(N*k*T) 542
- V/(N*.025) 543
- Is the Initial Approximation 544
- Close Enou 544
- STEPGMIN 545
- Bias Point and DC 546
- Switches 547
- Transient Analysis B 550
- .TRAN/OP 551
- Parasitic Capacitances 552
- Inductors and Transformers 552
- Junction 553
- ERROR 554
- 16 Conver 555
- Index-10 565
- Index-11 566
- Index-12 567
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